This file contains directory description of this CD project: Technical report folder -Project.doc: Technical Report documenting the details design (doc) -Project.pdf: Technical Report documenting the details design (pdf) poster: poster folder -Poster.ppt: Technical Poster Presentation xilinx: xilinx tools -spartan4k.exe: Xilinx Project Navigator, Classic Version Resources: C programming tools -i2c.c: C program for testing the system -i2c.h: Header file of i2c.c -cstart.s: A assembly wrapper for C code. -format_hex.c: a stand-alone program to extract Xilinx Programming Stream from a bit file, for running on a PC not the actual board -i2c_spartan_cfg.s: an assembly function to program the Spartan chip. -i2c_fpga_hex.s: Contains the Spartan programming Stream created by format_hex.c -header.s: Contains port address definitions. I2Cprotocol_lib: Project folder, containing all library source for HDL Designer. ****** Description of I2Cprotocol_lib folder *********** Open the project folder using HDL Designer, there are the following modules: ---------------------------------i2c interface------------------------------- -i2c_controller: i2c controller interface (i2c_controller_behave.vhd) -i2c_controller_tb: testbench schematic for i2c_controller -i2c_controller_tester: tester file for i2c_controller ---------------------------------microcontroller interface------------------- -micro_intf: microcontroller interface (micro_intf_behavioural.vhd) -micro_intf_tb: testbench schematic for micro_intf -micro_intf_tester: tester file for micro_intf ---------------------------------system interface---------------------------- -system: schematic view of the whole system (connecting microcontroller and i2c interface) ---------------------------------10 bit counter interface--------------------------- -up_cnt_10bit: a counter interface (up_cnt_8bit_behave.vhd) -up_cnt_10bit_tb: testbench schematic for counter -up_cnt_10bit_tester: tester file for counter ---------------------------------8 bit shift register interface ------------------- -shift8: shift register interface (shift_reg.vhd) -shift8_tb: testbench schematic for shift register -shift8_tester: tester file for shift register ---------------------------------System test with an i2c Slave model--------------------------------------- --in this test, an i2c slave model (an i2c memory) is connected to the system, and testing is carried out-- -test1: schematic of system testing with an i2c slave model. ie connecting system interface with an i2c slave model -test1_tb: testbench for system testing -test1_tester: tester file for testing system ---------------------------------i2c Slave model------------------------------------- -i2c_slave_model: an i2c slave model written in verilog (Downloaded from: http://www.opencores.org/projects/i2c/) ---------------------------------Open drain model----------------------------------- -open_drain: open drain model, modelling pull up network --------------------------------System test, without i2c slave model--------------------- --in this test, no i2c slave model is needed, instead, the tester file will emulate an i2c slave-- -systemTest: schematic of system testing -systemTest_tb: testbench for system testing -systemTest_tester: tester file for system testing ******************************************************************************************************** Procedure for generating a system bit file for loading into the Spartan-XL 1) Procedure for specifying system clock frequency.The default system clock frequency is 32 MHz, to use different system clock frequency, change the clock frequency generic definition by following these steps: -Open the project in HDL Designer -Click on the plus sign of system module under Design Units -Double click on symbol to open up the system interface -Right click on the system symbol and choose Object Properties -Change to desired frequency under generic declarations (note that a clock divider is used from the the system clock, thus need to change clk_freq to half the system clock, ie, if the system clock is 20 Hhz, change clk_freq to 10) -After doing these steps,back to symbol window,and regenerate a system file under Tasks, choose Generate 2) Procedure for synthesis and optimisation with Leonardo (generating a edf file) -Open the project in HDL Designer -From the HDL Designer interface, choose system module under Design Units on the left. -Double click on LeonardoSpectrum under My Tasks panel at the bottom right corner. -From LeonardoSpectrum window, choose SpartanXL under Technolody, S10xlVQ100 under devic. Design frequecy can also be specified. Make sure Add I/O pads box is ticked. Choose OK -From the main Leonardo window, under Technology, assign Global Reset to reset signal of the system. (Under Assign GSR, choose Manual and type in reset. Also from Technology, choose Advanced Settings at the bottom, Tick Fast Output buffers untick Global Buffers. -From here, run optimise using Optimise option and write an edf file from Output option 3) Procedure for placement and routing with Xilinx Project Navigator (generating a bit file) -Creat a new project in Xilinx Project Navigator -Add the edf file geneated by Leonardo into the project. -Double click on Implement the design -Right click on Generate Programming File, choose Properties, then Configurations Options, tick the Enable Express Mode Bitstream box -Double click on Generate Programming File, a bit will be generated in the xilinx directory ********************************************************************************************************************** I2C_update: Update design files: Folder I2C_update, contains an improved version of the system,however the improvement seems to work on simulation only, testing on actual hardware render unsuccessfully. This version of the system waits for the microcontroller to write new data before it transfer the next byte. Improvement on master receiver has not been done.