Index of /dsl-cdrom/unsw/projects/nulling

 Name                    Last modified      Size  Description
 Parent Directory                             -   
 Nulldesign.zip          22-Feb-2006 10:53  1.9M  
 Poster.ppt              02-Mar-2005 23:25  635K  
 disharray.jpg           02-Mar-2005 05:38   47K  
 sysstruct.jpg           02-Mar-2005 04:35   28K

Companion CD-ROM Nulling Directory

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Companion CD-ROM: /unsw/projects/nulling directory

The /unsw/projects/nulling directory contains the implementation details for the "Antenna Arrays for Adaptive Nulling" project.

This project was developed by Arnon Politi, in January 2005, as part of the Taste of Research Summer Scholarship.

Project Title

Antenna Arrays for Adaptive Nulling

Project Description

The aim of this project is to increase the signal-to-interference ratio of a received signal using an array of receiving antennas and computing a suitable weighted sum of the waveforms observed by these antennas. The system’s job is to find the optimal weights that would maximize the signal-to-interference ratio as an on-going process in order to adapt to the changing surrounding interference.

This project is based on the article “VLSI Systolic Arrays for Adaptive Nulling” by C. M. Rader (July 1996, IEEE Signal Processing Magazine, pp. 29-49).

System Structure

The inputs to the system are the waveforms received by the N antenna elements. These inputs are assumed to have been down-converted, sampled and digitized, feeding the system with digital complex samples. These samples are then passed to both parts of the system: The first part computes the weighted sum of the current samples using the optimal weights determined from previous samples, and the second part, which uses these samples in order to adapt future weights.

The block diagram of the components implemented by this project is as follows:

Project Implementation

The project was designed to be implemented on Altera’s APEX DSP Development Board using the Quartus II software. It had been simulated and tested successfully in software using random input data. The design utilizes about 4,500 logic elements per Supercell out of 51,800 elements available on the board. In the current implementation, the number of Supercells needed is the same as the number of input antennas. Improvement to the design can made so that only half as many Supercells are needed. The system works at 16MHz clock frequency, one sample fed into the system per clock cycle.